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The USRP X3xx Series consists of the X300 and X310—high-performance software defined radios built around a Xilinx Kintex-7 FPGA. They feature two interchangeable RF daughterboard slots, dual SFP+ ports for 1 GigE or 10 GigE connectivity, and an optional PCIe (MXI) interface for near-zero latency host connections. With up to 160 MHz of RF bandwidth at 16-bit samples and supported master clock rates of 200 MHz and 184.32 MHz, the X3xx Series is the foundation for demanding lab, field, and production deployments.

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Supported Models

X300

Xilinx Kintex-7 XC7K325T FPGA. Two daughterboard slots (A and B). Dual SFP+ + optional PCIe.

X310

Xilinx Kintex-7 XC7K410T FPGA (larger). Two daughterboard slots (A and B). Dual SFP+ + optional PCIe. Higher FPGA resource budget for larger RFNoC designs.

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Features

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Hardware Capabilities

  • 2 transceiver card slots — 2×2 MIMO out of the box
  • Dual SFP+ Transceivers — 1 GigE or 10 GigE
  • PCIe over cable (MXI) — Gen1 ×4 via NI PCIe-8371 or ExpressCard-8360B
  • External PPS input & output
  • External reference input & output: 10 MHz, 11.52 MHz, 23.04 MHz, or 30.72 MHz
  • Supported master clock rates: 200 MHz (default) and 184.32 MHz
  • Variable daughterboard clock rates
  • External GPIO connector (front panel) with UHD API control
  • On-board USB JTAG programmer
  • Internal GPSDO option

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FPGA Capabilities

  • 2 RX DDC chains and 2 TX DUC chains
  • Timed commands in FPGA
  • Timed sampling in FPGA
  • Up to 160 MHz of RF bandwidth with 16-bit samples
  • RFNoC capable

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Getting Started

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Assembling the X300/X310

  1. Remove the two Phillips screws from the top cover.
  2. Insert the daughterboards into slots A and B; optionally screw them to the motherboard.
  3. Connect RF cables from the daughterboard connectors to the labeled front-panel SMA ports.
  4. If installing an internal GPSDO, follow the GPSDO installation guide and connect an external GPS antenna to the rear GPS ANT connector.
  5. Insert a 1 GigE SFP+ transceiver into Ethernet Port 0 and connect the X3xx to your host.
  6. Connect the power supply and power on the device.

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Network Connectivity

An unconfigured X3xx defaults to 192.168.10.2 on 1 GigE. Set your host interface to 192.168.10.1 and verify: 
ping 192.168.10.2
uhd_find_devices
uhd_usrp_probe --args addr=192.168.10.2
If uhd_usrp_probe reports FPGA version warnings, update the FPGA image before proceeding.

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Updating the FPGA

# Download latest images
uhd_images_downloader

# Flash via Ethernet (auto-detect image type)
uhd_image_loader --args="type=x300,addr=192.168.10.2"

# Flash a specific flavor
uhd_image_loader --args="type=x300,addr=192.168.10.2,fpga=HG"

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Connection Methods

Insert a 1 Gigabit SFP transceiver into Ethernet Port 0. Connect to your host with a standard Ethernet cable.Default device IP address: 192.168.10.2Set the host interface to a static address in the same subnet (e.g., 192.168.10.1).
auto usrp = uhd::usrp::multi_usrp::make("type=x300,addr=192.168.10.2");

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FPGA Image Flavors

The X3xx ships two SFP+ ports; the FPGA image determines their behavior:
FlavorSFP+ Port 0SFP+ Port 1
HG (default)1 GigE10 GigE
XG10 GigE10 GigE
HA1 GigEAurora
XA10 GigEAurora
FPGA images are distributed in two formats:
  • LVBITX — for use over PCIe and Ethernet
  • BIT — for use over Ethernet and JTAG

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Master Clock Rate

The X3xx generates a single master clock rate per motherboard. Supported values:
  • 200 MHz (default; required for TwinRX daughterboard)
  • 184.32 MHz
Set the clock rate at initialization using the device argument: 
// 184.32 MHz master clock rate
auto usrp = uhd::usrp::multi_usrp::make("type=x300,master_clock_rate=184.32e6");
usrp->set_rx_rate(30e6); // coerced to 30.72e6 (= 184.32e6 / 6)
std::cout << usrp->get_rx_rate() << std::endl; // Prints 30720000
The X3xx does not support changing the master clock rate after initialization via set_master_clock_rate(). To switch rates, destroy the USRP object and recreate it with the new master_clock_rate argument.

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Supported Daughterboards

The X3xx accepts all standard USRP daughterboards in its two slots (A and B). Popular choices include:
DaughterboardFrequency RangeBandwidthNotes
WBX50 MHz – 2.2 GHz40 MHz (WBX) / 120 MHz (WBX-120)Full-duplex
SBX400 MHz – 4.4 GHz40 MHz / 120 MHzFull-duplex
CBX1.2 GHz – 6 GHz40 MHz / 120 MHzFull-duplex
UBX10 MHz – 6 GHz40 MHz / 160 MHzFull-duplex; requires dboard clock ≤ 20 MHz below 1 GHz
OBX10 MHz – 8.4 GHz160 MHzFull-duplex
TwinRX10 MHz – 6 GHz—2-channel RX only; requires 200 MHz MCR
BasicRX / LFRX—250 MHz / 66 MHzNo tuning elements
DBSRX2800 MHz – 2.3 GHz8–80 MHzSet dboard clock to 100 MHz
TVRX250 MHz – 860 MHzUp to 10 MHzSet dboard clock to 100 MHz
When using daughterboards at frequencies below 1 GHz with the UBX, reduce the daughterboard clock to 20 MHz for optimal phase synchronization and RF performance: dboard_clock_rate=20e6.

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Synchronization with OctoClock

To synchronize multiple X3xx devices, connect an OctoClock (CDA-2990) to distribute a shared 10 MHz reference and 1 PPS signal: 
auto usrp = uhd::usrp::multi_usrp::make(
    "type=x300,addr=192.168.10.2,clock_source=external,time_source=external");
The external reference clock input accepts 10 MHz, 11.52 MHz, 23.04 MHz, or 30.72 MHz. If using a non-10 MHz reference, provide the system_ref_rate argument: 
auto usrp = uhd::usrp::multi_usrp::make(
    "type=x300,addr=192.168.10.2,system_ref_rate=30.72e6,clock_source=external");

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Device Arguments

KeyDescriptionExample
addrIPv4 address of primary SFP+ portaddr=192.168.10.2
second_addrIPv4 address of secondary SFP+ portsecond_addr=192.168.40.2
resourceNI-RIO resource name (PCIe)resource=RIO0
master_clock_rateMaster clock rate in Hzmaster_clock_rate=184.32e6
dboard_clock_rateDaughterboard reference clock in Hzdboard_clock_rate=20e6
system_ref_rateExternal reference clock frequencysystem_ref_rate=30.72e6
time_sourcePPS sourcetime_source=external
clock_sourceReference clock sourceclock_source=external
fpgaSelect FPGA image flavor (PCIe only)fpga=HG
force_mtuManually set network MTUforce_mtu=8000

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Using the X3xx from UHD

// Single device via 1 GigE
auto usrp = uhd::usrp::multi_usrp::make("type=x300,addr=192.168.10.2");

// Two channels, TwinRX on slot A
usrp->set_rx_subdev_spec("A:RX1 A:RX2");

// Multiple RX channels with different antennas
usrp->set_rx_subdev_spec("A:RX1 A:RX2");
usrp->set_rx_rate(10e6, uhd::usrp::multi_usrp::ALL_CHANS);

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Front Panel Reference

Key front-panel indicators:
IndicatorMeaning
JTAG USBOn-board USB-JTAG programmer port
TX/RX LED (RF A)Data streaming on TX/RX channel, daughterboard A
RX2 LED (RF A)Data streaming on RX2 channel, daughterboard A
REF LEDExternal reference clock locked
PPS LEDPulses once per second on valid PPS signal
GPS LEDGPS reference locked (GPSDO option)
LINK LEDHost computer communicating with device

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Troubleshooting

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”No Control Response” Error

This error typically means the host IP address is on a different subnet than the USRP. Verify that your host interface is set to the correct static IP (e.g., 192.168.10.1 for 1 GigE Port 0).

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Firewall Blocking Discovery

Device discovery uses UDP broadcast. If uhd_find_devices returns nothing, allow UDP source port 49152 through your firewall, or specify the device IP address directly.

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PCIe Not Enumerating (Linux)

Start the NI device manager service: 
sudo niusrprio_pcie start
lspci -k -d 1093:c4c4  # Verify device is detected

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Corrupt EEPROM Recovery

usrp_burn_mb_eeprom --args="type=x300,recover_mb_eeprom,disable_adc_self_test" \
                    --values="revision=<NUM>"
Power-cycle the device after running this command.

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Additional Resources

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