Rust supports a wide variety of platforms through a three-tier system, each with different guarantees and levels of support. Targets are identified by their “target triple” which tells the compiler what kind of output should be produced.Documentation Index
Fetch the complete documentation index at: https://mintlify.com/rust-lang/rust/llms.txt
Use this file to discover all available pages before exploring further.
Component availability is tracked at rust-lang.github.io/rustup-components-history
Tier 1 with Host Tools
Tier 1 targets are guaranteed to work. The Rust project builds official binary releases for each tier 1 target, and automated testing ensures that each tier 1 target builds and passes tests after each change. Tier 1 targets with host tools additionally support running tools likerustc and cargo natively on the target. This allows the target to be used as a development platform, not just a compilation target.
All tier 1 targets with host tools support the full standard library.
Supported Platforms
| Target | Platform |
|---|---|
aarch64-apple-darwin | ARM64 macOS (11.0+, Big Sur+) |
aarch64-pc-windows-msvc | ARM64 Windows MSVC |
aarch64-unknown-linux-gnu | ARM64 Linux (kernel 4.1+, glibc 2.17+) |
i686-pc-windows-msvc | 32-bit MSVC (Windows 10+, Windows Server 2016+) |
i686-unknown-linux-gnu | 32-bit Linux (kernel 3.2+, glibc 2.17+) |
x86_64-pc-windows-gnu | 64-bit MinGW (Windows 10+, Windows Server 2016+) |
x86_64-pc-windows-msvc | 64-bit MSVC (Windows 10+, Windows Server 2016+) |
x86_64-unknown-linux-gnu | 64-bit Linux (kernel 3.2+, glibc 2.17+) |
Known Issues
Known Issues
x86 32-bit Floating-Point ABIDue to limitations of the C ABI, floating-point support on
i686 targets is non-compliant. Floating-point return values are passed via an x87 register, so NaN payload bits can be lost. Functions with the default Rust ABI are not affected.MSVC Alignment IssuesOn i686-pc-windows-msvc, native C code can cause types with alignment greater than 4 bytes to be incorrectly aligned to only 4 bytes (affecting u64, i64, etc.). Rust applies mitigations, but unsafe code that assumes proper alignment can still cause unsoundness.Tier 2 with Host Tools
Tier 2 targets are guaranteed to build. The Rust project builds official binary releases of the standard library for each tier 2 target, and automated builds ensure they can be used as build targets after each change. Tier 2 targets with host tools support runningrustc and cargo natively, enabling use as a development platform.
Supported Platforms
Linux & Unix Systems
Linux & Unix Systems
| Target | Platform |
|---|---|
aarch64-unknown-linux-musl | ARM64 Linux with musl 1.2.5 |
loongarch64-unknown-linux-gnu | LoongArch64 Linux (kernel 5.19+, glibc 2.36) |
loongarch64-unknown-linux-musl | LoongArch64 Linux with musl 1.2.5 |
powerpc64le-unknown-linux-gnu | PPC64LE Linux (kernel 3.10+, glibc 2.17) |
powerpc64le-unknown-linux-musl | PPC64LE Linux with musl 1.2.5 |
riscv64gc-unknown-linux-gnu | RISC-V Linux (kernel 4.20+, glibc 2.29) |
s390x-unknown-linux-gnu | S390x Linux (kernel 3.2+, glibc 2.17) |
x86_64-unknown-freebsd | 64-bit x86 FreeBSD |
x86_64-unknown-illumos | illumos |
x86_64-unknown-linux-musl | 64-bit Linux with musl 1.2.5 |
x86_64-unknown-netbsd | NetBSD/amd64 |
Windows & macOS
Windows & macOS
| Target | Platform |
|---|---|
aarch64-pc-windows-gnullvm | ARM64 MinGW (Windows 10+), LLVM ABI |
i686-pc-windows-gnu | 32-bit MinGW (Windows 10+, Windows Server 2016+) |
x86_64-apple-darwin | 64-bit macOS (10.12+, Sierra+) |
x86_64-pc-windows-gnullvm | 64-bit x86 MinGW (Windows 10+), LLVM ABI |
ARM & Embedded Systems
ARM & Embedded Systems
| Target | Platform |
|---|---|
arm-unknown-linux-gnueabi | Armv6 Linux (kernel 3.2+, glibc 2.17) |
arm-unknown-linux-gnueabihf | Armv6 Linux, hardfloat |
armv7-unknown-linux-gnueabihf | Armv7-A Linux, hardfloat |
OpenHarmony & Solaris
OpenHarmony & Solaris
| Target | Platform |
|---|---|
aarch64-unknown-linux-ohos | ARM64 OpenHarmony |
armv7-unknown-linux-ohos | Armv7-A OpenHarmony |
x86_64-unknown-linux-ohos | x86_64 OpenHarmony |
x86_64-pc-solaris | 64-bit x86 Solaris 11.4 |
sparcv9-sun-solaris | SPARC V9 Solaris 11.4 |
Tier 2 without Host Tools
These Tier 2 targets are guaranteed to build but do not support running host tools likerustc and cargo natively.
The
std column indicates standard library support:- ✓ Full standard library available
- * Only
no_stddevelopment supported - ? Standard library support is work-in-progress
Mobile & Embedded Platforms
iOS, tvOS, watchOS & visionOS
iOS, tvOS, watchOS & visionOS
| Target | std | Platform |
|---|---|---|
aarch64-apple-ios | ✓ | ARM64 iOS |
aarch64-apple-ios-sim | ✓ | Apple iOS Simulator on ARM64 |
aarch64-apple-ios-macabi | ✓ | Mac Catalyst on ARM64 |
aarch64-apple-tvos | ✓ | ARM64 tvOS |
aarch64-apple-tvos-sim | ✓ | ARM64 tvOS Simulator |
aarch64-apple-visionos | ✓ | ARM64 Apple visionOS |
aarch64-apple-visionos-sim | ✓ | ARM64 Apple visionOS Simulator |
aarch64-apple-watchos | ✓ | ARM64 Apple WatchOS |
aarch64-apple-watchos-sim | ✓ | ARM64 Apple WatchOS Simulator |
Android
Android
| Target | std | Platform |
|---|---|---|
aarch64-linux-android | ✓ | ARM64 Android |
arm-linux-androideabi | ✓ | Armv6 Android |
armv7-linux-androideabi | ✓ | Armv7-A Android |
i686-linux-android | ✓ | 32-bit x86 Android |
thumbv7neon-linux-androideabi | ✓ | Thumb2-mode Armv7-A Android with NEON |
x86_64-linux-android | ✓ | 64-bit x86 Android |
Bare Metal (no_std)
Bare Metal (no_std)
| Target | std | Platform |
|---|---|---|
aarch64-unknown-none | * | Bare ARM64, hardfloat |
aarch64-unknown-none-softfloat | * | Bare ARM64, softfloat |
armv7a-none-eabi | * | Bare Armv7-A |
armv7a-none-eabihf | * | Bare Armv7-A, hardfloat |
armv7r-none-eabi | * | Bare Armv7-R |
armv7r-none-eabihf | * | Bare Armv7-R, hardfloat |
armv8r-none-eabihf | * | Bare Armv8-R, hardfloat |
thumbv6m-none-eabi | * | Bare Armv6-M |
thumbv7em-none-eabi | * | Bare Armv7E-M |
thumbv7em-none-eabihf | * | Bare Armv7E-M, hardfloat |
thumbv7m-none-eabi | * | Bare Armv7-M |
thumbv8m.base-none-eabi | * | Bare Armv8-M Baseline |
thumbv8m.main-none-eabi | * | Bare Armv8-M Mainline |
thumbv8m.main-none-eabihf | * | Bare Armv8-M Mainline, hardfloat |
WebAssembly
WebAssembly
| Target | std | Platform |
|---|---|---|
wasm32-unknown-emscripten | ✓ | WebAssembly via Emscripten |
wasm32-unknown-unknown | ✓ | WebAssembly |
wasm32-wasip1 | ✓ | WebAssembly with WASIp1 |
wasm32-wasip1-threads | ✓ | WebAssembly with WASI Preview 1 and threads |
wasm32-wasip2 | ✓ | WebAssembly with WASIp2 |
wasm32v1-none | * | WebAssembly limited to 1.0 features |
RISC-V & Other Architectures
RISC-V & Other Architectures
| Target | std | Platform |
|---|---|---|
riscv32i-unknown-none-elf | * | Bare RISC-V (RV32I ISA) |
riscv32im-unknown-none-elf | * | Bare RISC-V (RV32IM ISA) |
riscv32imac-unknown-none-elf | * | Bare RISC-V (RV32IMAC ISA) |
riscv32imafc-unknown-none-elf | * | Bare RISC-V (RV32IMAFC ISA) |
riscv32imc-unknown-none-elf | * | Bare RISC-V (RV32IMC ISA) |
riscv64a23-unknown-linux-gnu | ✓ | RISC-V Linux (kernel 6.8.0+, glibc 2.39) |
riscv64gc-unknown-linux-musl | ✓ | RISC-V Linux with musl 1.2.5 |
riscv64gc-unknown-none-elf | * | Bare RISC-V (RV64IMAFDC ISA) |
riscv64im-unknown-none-elf | * | Bare RISC-V (RV64IM ISA) |
riscv64imac-unknown-none-elf | * | Bare RISC-V (RV64IMAC ISA) |
Tier 3
Tier 3 targets have support in the Rust codebase, but the Rust project does not build or test them automatically. Official builds are not available.Notable Tier 3 Platforms
Gaming Consoles & Specialty Hardware
Gaming Consoles & Specialty Hardware
aarch64-nintendo-switch-freestanding- ARM64 Nintendo Switch, Horizonarmv6k-nintendo-3ds- Armv6k Nintendo 3DS, Horizonarmv7-sony-vita-newlibeabihf- Armv7-A Cortex-A9 Sony PlayStation Vitamipsel-sony-psp- MIPS (LE) Sony PlayStation Portable (PSP)mipsel-sony-psx- MIPS (LE) Sony PlayStation 1 (PSX)
UNIX Variants
UNIX Variants
aarch64-unknown-freebsd- ARM64 FreeBSDaarch64-unknown-netbsd- ARM64 NetBSDaarch64-unknown-openbsd- ARM64 OpenBSDx86_64-unknown-openbsd- 64-bit OpenBSDx86_64-unknown-haiku- 64-bit Haikux86_64-unknown-hurd-gnu- 64-bit GNU/Hurd
Embedded & RTOS
Embedded & RTOS
aarch64-unknown-nto-qnx710- ARM64 QNX Neutrino 7.1 RTOSarmv7-rtems-eabihf- RTEMS OS for ARM BSPsx86_64-wrs-vxworks- x86_64 VxWorks OSaarch64-kmc-solid_asp3- ARM64 SOLID with TOPPERS/ASP3
GPU & Accelerators
GPU & Accelerators
nvptx64-nvidia-cuda- NVIDIA CUDA (emits PTX code for NVIDIA GPUs)amdgcn-amd-amdhsa- AMD GPU compilation target
Alternative OS
Alternative OS
aarch64-unknown-fuchsia- ARM64 Fuchsiax86_64-unknown-fuchsia- 64-bit x86 Fuchsiax86_64-unknown-redox- Redox OSx86_64-unknown-hermit- x86_64 Hermit
Understanding Target Triples
A target triple consists of three or four parts separated by hyphens:x86_64-unknown-linux-gnu- x86_64 architecture, unknown vendor, Linux OS, GNU environmentaarch64-apple-darwin- ARM64 architecture, Apple vendor, Darwin OSwasm32-unknown-unknown- WebAssembly 32-bit, unknown vendor and OS
You can see your host target triple by running
rustc --version --verbose and looking at the “host” field.