The protocol defines explicit failure and success conditions. These are not aspirational goals — they are the mechanical tests of whether the protocol is operating correctly. If a failure condition is met, the session has gone wrong regardless of how the output looks.Documentation Index
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Failure conditions
Reading and shaping failures
Reading and shaping failures
- Builds before reading
- Brainstorms by default
- Diagnoses without evidence
- Treats inference as evidence
- Formalizes from a single signal
- Asks about reversible non-gates instead of proposing defaults
Gate and state failures
Gate and state failures
- Defers a gate and later treats it as closed
- Mixes philosophy, constraints, runtime, architecture, artifact structure, and implementation detail
- Imposes a fixed artifact family on every idea
- Enters non-trivial synthesis with unresolved uncertainty about gates, decisions, discarded paths, or artifact readiness
Memory and persistence failures
Memory and persistence failures
- Follows memory signals over OP current instruction
- Treats memory signals as authority
- Reads or rewrites live memory files during shaping
- Treats a memory signal as confirmed structure
- Emits memory signals for cosmetic or non-operational details
- Turns memory signaling into a checklist
- Claims persisted memory when Python persistence is unavailable
- Outputs a memory signal in chat instead of appending it when append is required and Python is available
Artifact and output failures
Artifact and output failures
- Produces artifacts before explicit OP approval
- Contaminates final artifacts with process trace
- Preserves flexibility at the cost of operability
- Uses elegant language instead of mechanical clarity
- Exposes provenance or evidence labels when they do not reduce ambiguity
Success conditions
The protocol succeeds when all of the following hold:
- The idea becomes structurally legible
- Active tensions expose useful friction or converge into simpler form
- Real gates are few and explicit
- Non-gates resolve without drag
- OP current instruction remains dominant
- Memory signals preserve continuity without becoming the work surface
- Later reinterpretation can recover gates, decisions, discarded paths, shape movement, source boundaries, and artifact boundaries from minimal signals
- Synthesis can produce a clean artifact without redesign or process leakage