Configure SoC Resources with the CFS System Planner

Documentation Index

Fetch the complete documentation index at: https://mintlify.com/analogdevicesinc/codefusion-studio/llms.txt

Use this file to discover all available pages before exploring further.

The System Planner is CodeFusion Studio’s central configuration dashboard. It provides a visual, interactive environment for configuring every aspect of your SoC: which peripherals are assigned to which cores, how pins are multiplexed, what the clock tree looks like, how memory is partitioned, and what the resulting register values will be. All configuration choices are stored in a .cfsconfig file alongside your project, and the System Planner translates those choices into ready-to-build source code via its Generate Code tab.

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Opening the System Planner

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Dashboard tabs

The System Planner dashboard is organized into the following tabs. Each tab focuses on a specific aspect of the system configuration.

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Workspace Projects table

Located at the bottom of the System Planner dashboard, the Workspace Projects table provides an at-a-glance overview of every core in the workspace and its current resource allocations. Use this table to track resource allocation across cores and ensure everything is properly configured before generating code. Click the chevron (>) in any cell to open the corresponding configuration page.

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Peripheral Allocation

The Peripheral Allocation tab lets you assign SoC peripherals to projects, configure their settings, and manage pin assignments — all from a single panel.

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Overview

The Peripheral Allocation view is divided into three main areas:

1. Filter options — Filter peripherals by allocation status: all, allocated, or available.
2. Peripheral list — Displays all available peripherals. Use this panel to allocate peripherals to a project.
3. Core Projects section — Shows each project with its assigned peripherals, signals, and pins.

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Assignment types

There are two types of peripheral assignments:

• Peripheral assignments: An entire peripheral (such as UART0 or I²C2) is assigned to a single project. That project has full responsibility for initializing the peripheral, handling interrupts, and managing its resources.
• Pin assignments: Some peripherals — such as GPIO — allow assignment at the individual pin level. Pins belonging to the same peripheral can be assigned to and managed independently by multiple projects.

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Allocate a peripheral

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Peripheral Settings sidebar

When you allocate a peripheral, the Peripheral Settings sidebar opens. From here you can:

• Add a Description to capture notes about the peripheral’s role (for example: “UART0 – Used for debug console output”).
• Assign pins by toggling signals on or off. If multiple pin options are available, select from a dropdown then toggle it on.
• Set configuration parameters specific to the peripheral (defined in the SoC data model, optionally extended by the plugin). Use Reset to Default to restore all settings.
• Specify code generation plugin options such as Zephyr chosen role or peripheral clock frequency.

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Limitations

Peripheral allocation constraints

• After a peripheral is allocated to a project, it must be removed before it can be allocated to another project.
• Certain peripherals can only be allocated to specific projects due to hardware constraints.
• If a peripheral is shared across multiple projects (such as GPIO0), the primary project is responsible for system-wide initialization, including configuring clock sources and frequencies.

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Resolve pin conflicts

If a conflict appears when a pin is enabled, a conflict icon is displayed next to the signal.

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Pin Config

The Pin Config tab provides a graphical pin multiplexing and function selection editor. It removes the tedious and error-prone elements of manual pin configuration and flags conflicts in real time.

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Key components

1. Peripheral list — Click a peripheral to view its associated signals.
2. Filter options — Search by name, or filter by Assigned, Available, or Conflicts status.
3. Pin Mux map — Visual representation of the current multiplexing configuration. Hover over a pin to view its assigned function. Zoom with the scroll wheel; drag with the left mouse button.
4. Assign pin — Toggle a pin on or off to enable or disable the signal assignment.
5. Configuration sidebar — Click the configure icon next to a signal to open settings for that pin.

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Assign a pin

Each expanded peripheral lists signals with their name and pin designation. Toggle the pin to on to assign a signal. This enables the pin in generated code and updates the mux map.

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Resolve conflicts

Conflicts occur when multiple signals are configured to use the same physical pin. They are shown as red circles in the mux map and red X icons in the peripheral list. To resolve a conflict, disable one of the functions assigned to that pin.

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Configuration sidebar

The configuration sidebar is available after the pin is assigned and its peripheral is allocated. The available fields depend on the signal type:

• GPIO signals expose all configuration options, including the attached function and code generation metadata (availability depends on firmware platform).
• Peripheral signals expose basic options such as pull-up/pull-down state and power supply.

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Clock Config

The Clock Config tab lets you configure clock sources, dividers, multiplexers, and output pins across the entire processor. It enforces hardware frequency constraints and provides error indicators when settings are out of range.

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Clock tree diagram

The visual clock tree is similar to the diagram found in the processor’s User Guide. Nodes represent cores, peripherals, pins, multiplexers, and clock scalers. Frequencies at each node are shown within the node itself.

• Hover over any node or line to view frequency and configuration details.
• Bold nodes and lines are enabled; faint nodes and lines are disabled.
• Scroll to zoom; drag to pan; click the fit-to-screen icon to resize the diagram to your window.

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Node types

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Configuring a clock node

Click any node in the diagram or the node list to open its configuration options. Only valid options are enabled by the tool. Changes are immediately reflected in the diagram.

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Clock errors

Nodes shown in red indicate an error that must be resolved before code generation:

• Frequency out of range — The frequency is above or below the hardware limits for that peripheral.
• Unconfigured value — A required setting has not been specified, such as an unspecified frequency at a pin input or an unset pin mux for a clock signal.

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Memory Allocation

The Memory Allocation tab enables partitioning of internal and external SoC memory. Use it to create memory partitions and assign specific blocks of RAM or Flash to cores, ensuring critical functions own the memory resources they need.

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Create a partition

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Edit or delete a partition

To edit, click a partition directly in the memory allocation bar, or locate it in the central view and click Configure. To delete, click Delete in the Edit Partition form, or use the delete icon in the central view.

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Registers

The Registers tab displays all register values produced by the current configuration and highlights registers that have been modified. Modified registers are marked with an asterisk (*).

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Search and filter

Use the Search field to locate registers by name or address. Use preset filters to view only modified or unmodified registers.

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View register details

Click a register name to inspect its bit-level contents:

1. Hexadecimal values — The current and reset hexadecimal values.
2. Binary values — The reset value in binary, with modified bits highlighted by a distinct border.
3. Field details — Click a bit group or register field to see its access type (R/W), bit range, and description.

This view is particularly useful for verifying that your peripheral, pin, and clock configurations produce the expected hardware register state before committing to code generation.