Pipeline diagram
Stage reference
Stage gates
Every transition between stages requires an explicit gate to pass. SuperAntigravity will not proceed until the condition is met.- Design → Plan. You explicitly approve the design document. Acknowledging it is not enough — you must say you approve it.
- Plan → Implement. The plan file exists and every task has exact file paths and commands.
- Implement → Review. All tasks in the plan are complete and the full test suite is green.
- Review → Ship. The code-reviewer agent returns a verdict of APPROVED or APPROVED WITH SUGGESTIONS. A verdict of CHANGES REQUIRED blocks the gate.
- Ship. The verification-before-completion skill passes and the finishing-a-development-branch skill executes the merge or PR.
Gates protect you from the most expensive mistake in software development: spending hours implementing something that was poorly defined. The 10–15 minutes a design takes consistently saves hours of rework.
Interrupt protocols
Three situations can interrupt an in-progress pipeline: Bug discovered mid-implementation. SuperAntigravity loads the systematic-debugging skill, fixes the bug, adds a regression test, then resumes the plan from where it left off. It does not start a new pipeline stage. Scope change requested. Implementation stops immediately. The scope change returns to/brainstorm — it does not get silently absorbed into the current plan. The existing plan is not modified without a new approved design.
Test suite fails catastrophically (more than 20 failures). SuperAntigravity loads the systematic-debugging skill and identifies the root cause of the mass failure before attempting individual fixes.
Explore each stage
/brainstorm
Turn vague ideas into approved designs before any code is written.
/plan
Write a detailed, bite-sized implementation plan before touching the codebase.
/implement
Drive feature implementation through TDD with per-task review gates.
/review
Validate implementation against the plan using specialist agents.
/git
Smart git operations with pre-ship verification and safe defaults.