These four sketches are structurally identical to the MSB-first variants, with one critical difference:Documentation Index
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LSBFIRST is passed to SPISettings instead of MSBFIRST. This means bit 0 — the least significant bit — is transmitted first on MOSI, inverting the bit sequence that appears on the wire. The clock mode, clock speed, sent byte, and wiring all remain exactly the same. Loading an LSB sketch back-to-back with its MSB counterpart on a logic analyzer instantly shows the waveform reversal.
What Changes with LSBFIRST
The byte being transmitted in all four sketches is0x62, which in binary is 0110 0010.
| Bit Order | Transmission Sequence (bit 7 → bit 0) | MOSI Waveform |
|---|---|---|
MSBFIRST | 0, 1, 1, 0, 0, 0, 1, 0 | Low, High, High, Low, Low, Low, High, Low |
LSBFIRST | 0, 1, 0, 0, 0, 1, 1, 0 | Low, High, Low, Low, Low, High, High, Low |
SPI.transfer(). No additional bit-reversal in software is needed.
Mode 0 — CPOL=0, CPHA=0
Clock idles LOW; data sampled on the rising edge. Bit 0 of0x62 is the first bit clocked out on MOSI.
SPI_Echo_LSB_Mode0.ino
Mode 1 — CPOL=0, CPHA=1
Clock idles LOW; data sampled on the falling edge. The bit sequence on MOSI is the same LSB-first order as Mode 0 — only the sampling edge shifts.SPI_Echo_LSB_Mode1.ino
Mode 2 — CPOL=1, CPHA=0
Clock idles HIGH; data sampled on the falling (leading) edge. SCK sits high before CS asserts, then transitions on the first clock pulse with MOSI already presenting bit 0.SPI_Echo_LSB_Mode2.ino
Mode 3 — CPOL=1, CPHA=1
Clock idles HIGH; data sampled on the rising (trailing) edge. The combination of LSB-first bit order and Mode 3 timing produces the most visually distinct waveform compared to the standard MSB-first Mode 0 baseline.SPI_Echo_LSB_Mode3.ino
When to Use LSBFIRST
Choosing the correct bit order for your slave device
Choosing the correct bit order for your slave device
The vast majority of SPI peripherals — sensors, displays, memory chips, ADCs — specify MSB-first transmission in their datasheets.
MSBFIRST should be your default.Use LSBFIRST only when the slave device’s datasheet explicitly states that the least significant bit is transmitted first. Common examples include certain shift registers and some older serial DACs. The datasheet will typically show a timing diagram labeling the first bit shifted in as “D0” or “LSB” rather than “D7” or “MSB”.Mismatched bit order is a silent failure. If the master sends MSB-first but the slave expects LSB-first (or vice versa), the received byte will be a bit-reversed version of the intended value. The SPI transaction will complete without errors, the Serial Monitor will show a plausible hex value, and no exception will be thrown — making this one of the harder bugs to diagnose without a logic analyzer. Always verify the MOSI waveform bit-by-bit against the expected binary value of 0x62 (0110 0010) when bring-up fails.LSBFIRST is implemented entirely in the ATmega328P SPI hardware — the DORD bit in the SPCR register controls transmission order. No extra wiring, additional shift registers, or software bit-reversal routines are required. Switching between MSBFIRST and LSBFIRST is a single-argument change in SPISettings(...) and takes effect immediately on the next SPI.beginTransaction() call.