SPI (Serial Peripheral Interface) is a synchronous, full-duplex serial communication protocol widely used in embedded systems. A single master device drives a shared clock line and exchanges data with one or more slave devices simultaneously — bits shift out on MOSI while bits shift in on MISO at exactly the same time. This makes SPI a natural fit for high-throughput peripherals such as sensors (IMUs, barometers), SPI flash and EEPROM memory, analog-to-digital converters (ADCs), and display drivers (LCD/TFT controllers).Documentation Index
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Use this file to discover all available pages before exploring further.
Bus Architecture
SPI uses a strict master/slave model. The master owns the clock — it is solely responsible for generating the SCK signal that gates every transfer. Slaves are passive; they only respond when addressed by the master pulling their individual Chip Select (CS) line LOW. The bus is full-duplex: every clock cycle the master shifts one bit out on MOSI and simultaneously shifts one bit in on MISO. There is no concept of a half-duplex turn-around delay. The clock (SCK) and data lines (MOSI and MISO) are shared across all slaves on the bus, but each slave has its own dedicated CS line. Only the slave whose CS is asserted LOW drives MISO; all others must keep their MISO pin in a high-impedance (tri-stated) state.Signal Lines
| Signal | Pin (Arduino UNO) | Direction | Description |
|---|---|---|---|
| SCK | 13 | Output (master) | Serial clock generated by the master; synchronises all data sampling |
| MOSI | 11 | Output (master) | Master Out Slave In — data travelling from master to slave |
| MISO | 12 | Input (master) | Master In Slave Out — data travelling from slave to master |
| CS | 10 | Output (master) | Chip Select — pulled LOW by the master to select the target slave |
CS is active LOW by convention: the slave is selected when CS is driven LOW and deselected when CS returns HIGH. Always verify the polarity in your specific slave’s datasheet — some devices label this pin
CE, SS, or \CS and a small number use active-HIGH logic.Why SPI?
Full Duplex
Master and slave exchange data simultaneously on every clock cycle — no half-duplex handshake overhead means maximum throughput in both directions at once.
High Speed
The ATmega328P on the Arduino UNO supports SPI clock speeds up to 16 MHz, far exceeding the 400 kHz maximum of I²C in fast mode. Perfect for streaming large payloads.
Simple Hardware
SPI requires no pull-up resistors, no open-drain drivers, and no address arbitration logic. Four wires and a direct point-to-point connection is all that is needed per slave.
Flexible Configuration
Four distinct clock modes (CPOL/CPHA combinations) and selectable bit order (MSBFIRST or LSBFIRST) let SPI adapt to virtually any peripheral’s timing requirements.
SPI Transaction Flow
Master asserts CS LOW
The master drives its CS output pin LOW, selecting the target slave and signalling the start of a transaction. All other slaves — whose CS lines remain HIGH — ignore the bus.
Master generates the clock on SCK
The master begins toggling SCK according to the configured SPI mode. The clock rate, polarity (CPOL), and phase (CPHA) are all set before the transaction starts via
SPI.beginTransaction().Data shifts on MOSI and MISO simultaneously
On each active clock edge, the master shifts the next data bit onto MOSI while the slave shifts its response bit onto MISO. Both devices read the incoming bit on the same edge. This continues for each byte transferred via
SPI.transfer().Explore Further
Modes & Timing
Understand CPOL and CPHA, the four SPI modes, and how to select the right mode for any slave device.
Pin Configuration
Complete Arduino UNO pin wiring, CS setup code, logic analyzer probe points, and common wiring mistakes to avoid.