The Simulation view lets you analyse circuit behaviour before physical prototyping — generating SPICE netlists for external tools and running in-browser frequency analysis to produce Bode plots for passive filter circuits. No server round-trip is required for frequency analysis; the computation runs entirely in the browser.Documentation Index
Fetch the complete documentation index at: https://mintlify.com/wtyler2505/ProtoPulse/llms.txt
Use this file to discover all available pages before exploring further.
What SPICE simulation does in ProtoPulse
ProtoPulse’s SPICE support covers two complementary workflows:- Netlist generation — exports a
.cirfile from your circuit design that you can load into LTspice, ngspice, or any compatible SPICE simulator. - In-browser frequency analysis — computes the transfer function of passive filter circuits and renders a Bode plot in real time, with a key-metrics summary panel.
simulation_results table so that re-opening the Simulation view shows your last result without re-running the computation.
ProtoPulse’s in-browser solver handles AC/frequency analysis for passive filter topologies. Transient analysis (
.TRAN) and DC sweep (.DC) require exporting a SPICE netlist and running it in an external simulator such as LTspice or ngspice. Full in-browser transient simulation is planned for a future release.Generating a SPICE netlist
Open the Simulation tab
Click Simulation in the main tab bar. The SPICE Simulation panel appears on the left side of the view.
Review your circuit
Confirm that your schematic has placed component instances, named nets, and defined component values (resistance, capacitance, etc.) in the component properties. The netlist generator reads these values directly from the circuit design.
Export the netlist
Navigate to the Exports tab and click Download on the SPICE Netlist (.cir) card. The file is generated server-side and downloaded immediately. You can also ask the AI: “Generate a SPICE netlist.”
Running AC/frequency analysis
The Frequency Analysis Panel computes the frequency response of passive filter circuits entirely in the browser. It evaluates the transfer function H(s) at 50 logarithmically-spaced points per decade across your chosen frequency range.Navigate to Frequency Analysis
Click Simulation in the tab bar, then select Frequency Analysis from the panel selector.
Choose a filter topology
Select one of the five supported filter topologies from the topology dropdown (see table below).
Enter component values
Fill in the required component values for your chosen topology. Values accept SI unit suffixes — see the SI suffix section below.
Set the frequency range
Enter a minimum and maximum frequency in Hz. The default sweep covers 1 Hz to 10 MHz.
Run the analysis
Click Analyze. The Bode plot renders immediately with magnitude (dB) and phase (degrees) plotted against frequency.
Review the summary panel
A summary panel below the plot shows key extracted metrics: DC gain, −3 dB cutoff frequency, resonant frequency, phase margin, and gain margin where applicable.
Reading Bode plots
The Bode plot displays two traces on a shared logarithmic frequency axis:| Trace | Units | What it shows |
|---|---|---|
| Magnitude | dB (20 · log₁₀|H(jω)|) | How much the circuit amplifies or attenuates a signal at each frequency |
| Phase | degrees, wrapped to [−180°, +180°] | Phase shift introduced by the circuit at each frequency |
- −3 dB point — The frequency where signal power is halved (0.707× amplitude). This is the cutoff frequency for low-pass and high-pass filters.
- Rolloff slope — First-order RC filters roll off at −20 dB/decade. Second-order RLC filters roll off at −40 dB/decade past the cutoff.
- Phase margin — For closed-loop stability analysis, the phase at the gain crossover frequency (where gain = 0 dB) must stay above 0°.
- Resonant peak — In RLC bandpass filters, the magnitude peaks sharply at the resonant frequency (ω₀ = 1/√LC).
Supported filter topologies
| Topology | Transfer function | Required values |
|---|---|---|
| RC low-pass | H(s) = 1 / (1 + sRC) | R, C |
| RC high-pass | H(s) = sRC / (1 + sRC) | R, C |
| RLC bandpass | H(s) = sL / (R + sL + 1/sC) | R, L, C |
| RLC low-pass | H(s) = (1/LC) / (s² + sR/L + 1/LC) | R, L, C |
| Generic 2nd order | H(s) = ω₀² / (s² + 2ζω₀s + ω₀²) | ω₀ (rad/s), ζ (damping ratio) |
SI suffix parsing
Component value fields accept standard SI suffixes so you can type values the way you would write them on a schematic:| Suffix | Multiplier | Example input | Parsed value |
|---|---|---|---|
k | ×10³ | 4k7, 10k | 4700 Ω, 10 000 Ω |
M | ×10⁶ | 2M2 | 2 200 000 Ω |
m | ×10⁻³ | 100m | 0.1 H |
u | ×10⁻⁶ | 2.2u, 100u | 2.2 µF, 100 µF |
n | ×10⁻⁹ | 100n, 47n | 100 nF, 47 nF |
p | ×10⁻¹² | 10p | 10 pF |
4k7 meaning 4.7 kΩ) is also supported, where the suffix acts as a decimal point.
How simulation results are cached
Every time you run a frequency analysis, the result is stored in thesimulation_results database table keyed to your project. When you return to the Simulation view, the last result is loaded automatically so you can continue reviewing it without re-running the analysis.
Results are invalidated when you modify your circuit design or change analysis parameters. Cached results are project-scoped — switching to a different project shows that project’s last simulation, not the current one.
Schematic Capture
Place components and draw nets to build the circuit you want to simulate.
Export Formats
Download SPICE netlists and other manufacturing files from the Output view.
Design Validation
Run DRC and ERC to catch errors before simulation or fabrication.
AI Assistant
Ask the AI to generate netlists or run frequency analysis on your design.