ProtoPulse’s Validation view runs automated checks across your design to catch problems before you commit to fabrication. It combines an Electrical Rule Check (ERC) for schematic correctness with a Design Rule Check (DRC) for PCB physical constraints, surfacing every finding with a severity level, affected component, human-readable description, and suggested fix.Documentation Index
Fetch the complete documentation index at: https://mintlify.com/wtyler2505/ProtoPulse/llms.txt
Use this file to discover all available pages before exploring further.
Two types of validation
ERC — Electrical Rule Check
The ERC validates the logical correctness of your schematic. It checks that your circuit is wired in a way that makes electrical sense, independent of any physical layout constraints. ERC runs from two places: the ERC Panel inside the Schematic view for immediate feedback while editing, and the Validation view for a full design-wide report. What ERC checks:| Rule | Default severity | What it detects |
|---|---|---|
| Unconnected pin | Warning | Pins with no connection and no no-connect marker placed |
| Shorted power | Error | Two or more power nets connected together |
| Floating input | Warning | Input pins with no driving source |
| Missing bypass capacitor | Warning | Power pins without a nearby decoupling capacitor |
| Driver conflict | Error | Multiple output drivers connected to the same net |
| No-connect connected | Warning | A no-connect marker that also has a net connected to it |
| Power net unnamed | Warning | Power nets that have not been assigned a name |
DRC — Design Rule Check
The DRC validates the physical layout of your PCB against manufacturing constraints. It checks that your traces, pads, and other copper features can actually be manufactured by a fab house without defects. What DRC checks:| Rule type | What it enforces |
|---|---|
min-trace-width | Copper traces meet the minimum width for the selected process |
min-clearance | Spacing between copper features (trace-to-trace, trace-to-pad) |
pad-size | Pad outer diameter and drill diameter meet minimum sizes |
annular-ring | Copper ring around a drilled hole is wide enough |
trace-to-edge | Traces stay a safe distance from the board edge |
solder-mask | Solder mask dam width and expansion around pads |
via-in-pad | Vias placed inside SMD pads (a DFM concern) |
silk-overlap | Silkscreen text or lines overlap copper pads |
courtyard-overlap | Component courtyards overlap each other |
pin-spacing | Pin pitch matches standard assembly equipment tolerances |
Issue severity levels
Every validation finding is assigned one of three severity levels:| Severity | Colour | Meaning |
|---|---|---|
| Error | Red | A critical problem that must be fixed before fabrication. For example: driver conflict on a net, or trace width below the fab minimum. |
| Warning | Yellow | A potential problem worth investigating. For example: no ESD protection on a USB-C port, or low-stock component. |
| Info | Blue | A suggestion or best practice. For example: consider adding a watchdog timer, or a reference designator convention to follow. |
What each issue shows
Every issue card in the Validation view displays:- Severity icon — colour-coded for instant triage
- Description — a plain-English explanation of the problem (e.g., “SPI bus contention possible without proper CS management”)
- Affected component — the reference designator or component name involved
- Suggested fix — a green-highlighted recommendation for resolving the issue
Resolving and dismissing issues
Marking an issue resolved: Hover over an issue card to reveal the Mark Resolved button. Click it to remove the issue from the list. A toast notification confirms the action. Use this after you have made a change in the schematic or layout that addresses the problem. Dismissing an issue: Right-click an issue card and select Dismiss Issue. You will be asked to confirm, because dismissing removes the issue without verifying that the underlying problem has been fixed. Use dismissal for issues you have consciously decided to accept (for example, an info-level suggestion that does not apply to your design). When all issues are resolved or dismissed, the Validation view displays a green “All Systems Nominal” message. Additional right-click options:- View in Architecture — jump to the Architecture view to see the affected component in context
- Copy Issue Details — copy the issue description to the clipboard
Manufacturer rule templates
Before sending your board to a fab house, apply the corresponding manufacturer rule template to validate your design against that fab’s actual capabilities. ProtoPulse ships with templates for the three most popular low-cost PCB services.What does each manufacturer template check?
What does each manufacturer template check?
- JLCPCB
- PCBWay
- OSHPark
ProtoPulse includes two JLCPCB templates:JLCPCB 2-Layer (standard PCB service):
JLCPCB 4-Layer (tighter tolerances on inner layers):
Via-in-pad, silk-overlap, courtyard-overlap, and solder-mask rules are enforced as warnings on both templates.
| Rule | Minimum value |
|---|---|
| Trace width | 0.127 mm (5 mil) |
| Trace clearance | 0.127 mm (5 mil) |
| Drill diameter | 0.3 mm |
| Pad outer diameter | 0.6 mm |
| Annular ring | 0.13 mm |
| Trace-to-edge clearance | 0.3 mm |
| Solder mask dam | 0.1 mm |
| Courtyard clearance | 0.25 mm |
| Rule | Minimum value |
|---|---|
| Trace width | 0.09 mm |
| Trace clearance | 0.09 mm |
| Drill diameter | 0.2 mm |
| Pad outer diameter | 0.6 mm |
| Annular ring | 0.13 mm |
Running validation via the UI vs via AI
- Via the UI
- Via the AI
Select a manufacturer template (optional)
Click Select Template and choose JLCPCB, PCBWay, or OSHPark if you want to validate against a specific fab’s rules.
Run DRC checks
Click the Run DRC Checks button. ProtoPulse analyses your design and populates the issues list.
Schematic Capture
Run ERC inline while editing your schematic in the ERC Panel.
Export Formats
The DRC gate validates critical errors before generating manufacturing files.
AI Tool Actions Reference
Full reference for the 9 AI validation tools including auto-fix and DFM.
Component Editor
Define accurate PCB footprints so DRC catches real clearance violations.