Design Rules

Design rules define the manufacturing constraints and electrical requirements for your PCB. The DRC (Design Rule Check) engine validates your layout against these rules to ensure manufacturability and correct operation.

Overview

KiCad’s design rule system is built around the DRC_ENGINE class (source/pcbnew/drc/drc_engine.h:131), which evaluates constraints and reports violations. Rules can be simple global settings or complex conditional expressions.

DRC Engine Architecture

DRC_ENGINE Class

// Source: pcbnew/drc/drc_engine.h:131
class DRC_ENGINE : public UNITS_PROVIDER
{
    BOARD* m_board;
    BOARD_DESIGN_SETTINGS* m_designSettings;
    std::vector<DRC_TEST_PROVIDER*> m_testProviders;
    
    void RunTests( PROGRESS_REPORTER* aProgressReporter );
    std::vector<std::shared_ptr<DRC_ITEM>> GetViolations();
    void EvalRules( DRC_CONSTRAINT_T aConstraintType,
                   const BOARD_ITEM* a,
                   const BOARD_ITEM* b,
                   PCB_LAYER_ID aLayer,
                   REPORTER* aReporter );
};

Design Constraints

Clearance Rules

Minimum spacing between objects

Track Width

Trace width constraints

Via Size

Via diameter and drill limits

Differential Pairs

Coupled routing requirements

Rule Types

Clearance Constraints

Define minimum spacing between objects:

Copper Clearance
Hole to Hole
Edge Clearance
Courtyard Clearance

Electrical clearance between copper features:

// Tested by: drc_test_provider_copper_clearance.cpp
min_clearance: 0.2mm  // Typical for standard PCB

Applies between:

Track to track (different nets)
Track to pad
Pad to pad
Zone to any copper

Mechanical clearance between drilled holes:

// Tested by: drc_test_provider_hole_to_hole.cpp  
hole_to_hole: 0.5mm  // Typical mechanical limit

Prevents drill breakage and ensures mechanical integrity.

Distance from board edge:

// Tested by: drc_test_provider_edge_clearance.cpp
edge_clearance: 0.3mm  // Keep components away from edge

Component collision detection:

// Tested by: drc_test_provider_courtyard_clearance.cpp
// Ensures footprint courtyards don't overlap

Track Constraints

Control trace geometry:

min/opt/max

Minimum: 0.127mm (5 mil) typical for fine-pitchOptimal: 0.254mm (10 mil) for standard signalsMaximum: Unlimited (or limited for controlled impedance)

minimum

Copper ring around drilled holeTypical: 0.15mm minimum for standard PCBs

allowed

Permitted routing anglesCommon: 45° or 90° only (avoid arbitrary angles)

Via Constraints

// Tested by: drc_test_provider_via_diameter.cpp
struct VIA_DIMENSION
{
    int m_Diameter;     // Via pad diameter
    int m_Drill;        // Drill hole size
};

Typical values:

Standard Via: 0.6mm pad, 0.3mm drill
Micro Via: 0.4mm pad, 0.2mm drill (laser drilled)
Large Via: 1.0mm+ for high current

Differential Pair Rules

For high-speed signals (USB, LVDS, etc.):

// Tested by: drc_test_provider_diff_pair_coupling.cpp
struct DIFF_PAIR_CONSTRAINT
{
    int gap;              // Spacing between traces
    int max_uncoupled;    // Maximum uncoupled length
    int width;            // Individual trace width
};

USB 2.0 typically requires:

Gap: 0.127mm (5 mil)
Width: 0.254mm (10 mil)
Impedance: 90Ω differential

Custom Design Rules

KiCad supports advanced rule syntax for complex constraints:

Rule File Format

Rules are defined in the .kicad_dru file or board settings:

(version 1)

# Global clearance rule
(rule "default clearance"
  (constraint clearance (min "0.2mm")))

# High-voltage clearance
(rule "HV clearance"
  (condition "A.NetClass == 'HV' || B.NetClass == 'HV'")
  (constraint clearance (min "2.0mm")))

# Power trace width
(rule "power width"
  (condition "A.NetClass == 'Power'")
  (constraint track_width (min "0.5mm")))

# USB differential pairs
(rule "USB diff pair"
  (condition "A.inDiffPair('/USB*')")
  (constraint diff_pair_gap (min "0.127mm") (opt "0.127mm"))
  (constraint diff_pair_width (min "0.254mm") (opt "0.254mm")))

Rule Conditions

Filter rules using expressions:

Net-based Conditions

A.NetName == 'GND'
A.NetClass == 'Power'
A.inDiffPair('/USB_*')

Layer Conditions

A.Layer == 'F.Cu'
A.isPlated()

Type Conditions

A.Type == 'Via'
A.Type == 'Track'
B.Type == 'Pad'

Property Conditions

A.hasProperty('PartNumber')
A.getProperty('Value') == '100nF'

DRC Test Providers

The DRC engine runs multiple specialized test providers:

Copper Clearance

Provider: drc_test_provider_copper_clearance.cppChecks spacing between all copper features on each layer.

Hole Size

Provider: drc_test_provider_hole_size.cppValidates drill diameters against manufacturing limits.

Track Width

Provider: drc_test_provider_track_width.cppEnsures all traces meet minimum/maximum width constraints.

Connectivity

Provider: drc_test_provider_connectivity.cppChecks for unconnected nets and starved thermals.

Schematic Parity

Provider: drc_test_provider_schematic_parity.cppVerifies PCB matches schematic netlist.

Silk Clearance

Provider: drc_test_provider_silk_clearance.cppPrevents silkscreen over pads and vias.

Text Dimensions

Provider: drc_test_provider_text_dims.cppValidates text size and stroke width.

Solder Mask

Provider: drc_test_provider_solder_mask.cppChecks solder mask clearance and bridging.

Running DRC

Interactive DRC

Run from the PCB editor:

Inspect → Design Rules Checker
Select test scope (entire board or specific area)
Choose which violations to check
Run tests and review violations
Navigate to errors from the violations panel

Batch DRC

Run DRC from command line or CI/CD:

kicad-cli pcb drc \
  --output report.txt \
  --format json \
  --severity-all \
  design.kicad_pcb

Violation Handling

The engine calls violation handlers for each error:

typedef std::function<void(
    const std::shared_ptr<DRC_ITEM>& aItem,
    const VECTOR2I& aPos,
    int aLayer,
    const std::function<void( PCB_MARKER* )>& aPathGenerator
)> DRC_VIOLATION_HANDLER;

Clearance Caching

For performance, clearance values are cached:

// Source: pcbnew/drc/drc_engine.h:42
struct DRC_OWN_CLEARANCE_CACHE_KEY
{
    KIID m_uuid;          // Item identifier
    PCB_LAYER_ID m_layer; // Layer being checked
};

// Cache stores computed clearance values
unordered_map<DRC_OWN_CLEARANCE_CACHE_KEY, int> m_clearanceCache;

Net Classes

Group nets with common requirements:

class NETCLASS
{
    wxString m_name;           // Net class name
    int m_clearance;           // Clearance requirement
    int m_trackWidth;          // Default track width  
    int m_viaDiameter;         // Via pad size
    int m_viaDrill;            // Via drill size
    int m_diffPairWidth;       // Diff pair trace width
    int m_diffPairGap;         // Diff pair spacing
};

Assign nets to classes in schematic or PCB editor. Classes provide default values that can be overridden by specific design rules.

Manufacturing Limits

Typical PCB manufacturer capabilities:

Standard PCB
Fine Pitch
HDI / Advanced

Minimum trace: 0.127mm (5 mil)
Minimum clearance: 0.127mm (5 mil)
Minimum drill: 0.3mm (12 mil)
Minimum annular ring: 0.15mm (6 mil)

Best Practices

Start Conservative

Begin with relaxed rules that match standard PCB capabilities. Tighten only where necessary for routing density or performance.

Use Net Classes

Group related nets (power, high-speed, differential pairs) into net classes. Apply class-specific rules rather than per-net rules.

Document Special Rules

Add comments in custom rules explaining the reasoning. Include links to datasheets or standards.

Test Early and Often

Run DRC frequently during layout. Fix violations incrementally rather than at the end.

Verify with Manufacturer

Confirm your design rules match your chosen PCB manufacturer’s capabilities before finalizing the design.

Advanced Features

Length Matching

Ensure equal trace lengths for timing-critical nets:

// Tested by: drc_test_provider_matched_length.cpp
rule "DDR length matching"
  (condition "A.NetClass == 'DDR'")
  (constraint length (min "50mm") (max "52mm"))
  (constraint skew (max "1mm"))  # Maximum length difference

Creepage and Clearance

For high-voltage designs:

// Tested by: drc_test_provider_creepage.cpp  
rule "mains creepage"
  (condition "A.NetClass == 'Mains' || B.NetClass == 'Mains'")
  (constraint creepage (min "3mm"))  # Surface path distance

Via Restrictions

Control via placement:

rule "no vias under BGA"
  (condition "B.Reference == 'U1'")
  (constraint disallow via)

Source Code References

// Main DRC engine
// Location: source/pcbnew/drc/drc_engine.h:131
class DRC_ENGINE : public UNITS_PROVIDER

// Individual test implementations  
// Location: source/pcbnew/drc/drc_test_provider_*.cpp
// Each file tests specific constraint types

// Rule parsing and evaluation
// Location: source/pcbnew/drc/drc_rule.h
class DRC_RULE

Next Steps

PCB Layout

Apply design rules during routing

Manufacturing Output

Generate fabrication files

Footprint Libraries

Design footprints meeting rules

Getting Started

Core Applications

Design Workflow

Advanced Features

Design Rules

Overview

DRC Engine Architecture

DRC_ENGINE Class

Design Constraints

Clearance Rules

Track Width

Via Size

Differential Pairs

Rule Types

Clearance Constraints

Track Constraints

Via Constraints

Differential Pair Rules

Custom Design Rules

Rule File Format

Rule Conditions

DRC Test Providers

Running DRC

Interactive DRC

Batch DRC

Violation Handling

Clearance Caching

Net Classes

Manufacturing Limits

Best Practices

Advanced Features

Length Matching

Creepage and Clearance

Via Restrictions

Source Code References

Next Steps

PCB Layout

Manufacturing Output

Footprint Libraries

​Overview

​DRC Engine Architecture

​DRC_ENGINE Class

​Design Constraints

Clearance Rules

Track Width

Via Size

Differential Pairs

​Rule Types

​Clearance Constraints

​Track Constraints

​Via Constraints

​Differential Pair Rules

​Custom Design Rules

​Rule File Format

​Rule Conditions

​DRC Test Providers

​Running DRC

​Interactive DRC

​Batch DRC

​Violation Handling

​Clearance Caching

​Net Classes

​Manufacturing Limits

​Best Practices

​Advanced Features

​Length Matching

​Creepage and Clearance

​Via Restrictions

​Source Code References

​Next Steps

PCB Layout

Manufacturing Output

Footprint Libraries

Overview

DRC Engine Architecture

DRC_ENGINE Class

Design Constraints

Rule Types

Clearance Constraints

Track Constraints

Via Constraints

Differential Pair Rules

Custom Design Rules

Rule File Format

Rule Conditions

DRC Test Providers

Running DRC

Interactive DRC

Batch DRC

Violation Handling

Clearance Caching

Net Classes

Manufacturing Limits

Best Practices

Advanced Features

Length Matching

Creepage and Clearance

Via Restrictions

Source Code References

Next Steps