Schematic Design

The schematic editor (Eeschema) is the core application for creating electronic circuit diagrams in KiCad. It manages hierarchical schematics, electrical connectivity, and generates netlists for PCB layout.

Overview

The schematic design workflow in KiCad revolves around the SCHEMATIC class (source/eeschema/schematic.h:87), which holds all data relating to one or more sheets in a hierarchical design.

Single Sheet

Simple designs with all components on one sheet

Hierarchical

Complex designs organized into multiple sheets

Creating a New Schematic

Initialize Schematic

Create a new schematic through the project manager or File menu. The schematic is initialized with a root sheet:

// Source: eeschema/schematic.h
class SCHEMATIC : public EDA_ITEM, public EMBEDDED_FILES
{
    SCH_SHEET* m_rootSheet;  // Virtual root containing all top-level sheets
    SCH_SHEET_PATH* m_currentSheet;  // Currently active sheet
};

Add Components

Place symbols from libraries onto the schematic canvas. Components are managed by the schematic editor frame (SCH_EDIT_FRAME).

Use the Add Symbol tool (A key)
Browse libraries using the symbol chooser
Place components with proper orientation and values

Connect Components

Create electrical connections using wires, buses, and labels:

Wires: Point-to-point connections (source/eeschema/bus-wire-junction.cpp)
Buses: Multi-signal connections with bus aliases
Labels: Net names for logical connections
Global Labels: Cross-sheet connections

Add Power Symbols

Connect power and ground symbols to establish power nets. Power symbols are special symbols marked with ENTRY_GLOBAL_POWER attribute.

Annotate References

Assign unique reference designators to all components:

// Source: eeschema/annotate.cpp
// Automatically assigns references like R1, R2, C1, etc.

The annotation system ensures no duplicate references exist in the design.

Hierarchical Design

Sheet Management

Hierarchical schematics use a tree structure with the SCH_SHEET class:

// Source: eeschema/schematic.h
SCH_SHEET_LIST BuildSheetListSortedByPageNumbers() const;
SCH_SHEET_LIST Hierarchy() const;  // Full flattened hierarchy

Use hierarchical sheets to organize complex designs into functional blocks. Each sheet can be reused multiple times with different instance data.

The hierarchy is maintained as a SCH_SHEET_PATH that tracks the current location:

SCH_SHEET_PATH& CurrentSheet() const { return *m_currentSheet; }
void SetCurrentSheet( const SCH_SHEET_PATH& aPath );

Electrical Rules Check (ERC)

Before moving to PCB layout, validate your schematic:

Run ERC

Execute electrical rules checking to find:

Unconnected pins
Conflicting power nets
Missing labels or references

Review Markers

ERC markers indicate potential issues in the design. Review and resolve all errors before proceeding.

Resolve Exclusions

Mark intentional violations as excluded:

std::vector<SCH_MARKER*> ResolveERCExclusions();
void RecordERCExclusions();

Connection Graph

KiCad builds a connection graph to analyze electrical connectivity:

// Source: eeschema/connection_graph.h
class CONNECTION_GRAPH
{
    // Manages net names, bus resolution, and connectivity analysis
};

The connection graph is recalculated when:

Components are added or removed
Wires or labels change
Hierarchy structure is modified

Variants

KiCad supports assembly variants for different product configurations:

wxString GetCurrentVariant() const;
void SetCurrentVariant( const wxString& aVariantName );
const std::set<wxString>& GetVariantNames() const;

Variants allow you to manage DNP (Do Not Place) status and alternate component values for different product builds.

File Format

Schematics are saved in .kicad_sch format (S-expression based):

(kicad_sch (version 20231120) (generator eeschema)
  (symbol (lib_id "Device:R") (at 100 100)
    (property "Reference" "R1")
    (property "Value" "10k")
  )
)

Best Practices

Organize with Hierarchy

Break complex designs into functional blocks using hierarchical sheets. Keep each sheet focused on a specific subsystem.

Use Bus Aliases

Define bus aliases for multi-signal connections:

std::shared_ptr<BUS_ALIAS> GetBusAlias( const wxString& aLabel ) const;
void AddBusAlias( std::shared_ptr<BUS_ALIAS> aAlias );

Consistent Naming

Use meaningful net names and consistent reference designator prefixes. Follow industry standards for power net names (+3V3, GND, etc.).

Document Your Design

Add text notes, title blocks, and revision history. Use symbol fields for datasheets and manufacturer part numbers.

Source References

// Main schematic container class
// Location: source/eeschema/schematic.h:87
class SCHEMATIC : public EDA_ITEM, public EMBEDDED_FILES, public PROJECT::_ELEM

// Schematic editor UI and tools
// Location: source/eeschema/sch_edit_frame.h:88
class SCH_EDIT_FRAME : public SCH_BASE_FRAME

// Electrical connectivity analysis
// Location: source/eeschema/connection_graph.h
class CONNECTION_GRAPH

Next Steps

Symbol Libraries

Manage and create symbol libraries

PCB Layout

Transfer your design to PCB layout

Design Rules

Configure electrical and physical rules

Manufacturing Output

Generate production files

Getting Started

Core Applications

Design Workflow

Advanced Features

Schematic Design

Overview

Single Sheet

Hierarchical

Creating a New Schematic

Hierarchical Design

Sheet Management

Sheet Navigation

Electrical Rules Check (ERC)

Connection Graph

Variants

File Format

Best Practices

Source References

Next Steps

Symbol Libraries

PCB Layout

Design Rules

Manufacturing Output

​Overview

Single Sheet

Hierarchical

​Creating a New Schematic

​Hierarchical Design

​Sheet Management

​Sheet Navigation

​Electrical Rules Check (ERC)

​Connection Graph

​Variants

​File Format

​Best Practices

​Source References

​Next Steps

Symbol Libraries

PCB Layout

Design Rules

Manufacturing Output

Overview

Creating a New Schematic

Hierarchical Design

Sheet Management

Sheet Navigation

Electrical Rules Check (ERC)

Connection Graph

Variants

File Format

Best Practices

Source References

Next Steps